A system on chip is a data processing device located on a single semi-conductor chip and capable of executing instructions stored in a memory unit on the chip. The instructions may be soft coded or hard coded. A system on chip may comprise multiple interconnected functional units, for example, one or more processor cores, one or more memory units, or input/output units for enabling the system on chip (SoC) to interact with its environment, e.g., via one or more antennas or via wired connections.
A SoC may comprise a buffer, e.g., a First-In-First-Out (FIFO) buffer or, e.g., a stack buffer, connected between a data source and a processing unit. The buffer may absorb an incoming flux of data, i.e. a data stream, while the processing unit is occupied. In many applications, a data source may send out a continuous stream of data which has to be received while the processing unit services the data source only when it is available, then emptying the data that has accumulated in the buffer.
A data source may be any hardware or software component that is capable of providing, e.g., generating or forwarding, a data stream. A processing unit may be any hardware or software component for processing the received data. For example, the data source may be an Ethernet port on the SoC. The processing unit may for example be a hardware accelerator arranged to carry out various processing actions on incoming packets from the data source. A buffer may for example be a FIFO buffer, a data stack, or any other memory structure capable of maintaining a write pointer for indicating a next available address for writing and a read pointer for indicating a next address to read from.
Such buffers may for example be implemented as on-chip static-random-access-memory (SRAM) units. The size of a buffer may be chosen so as to be able to absorb enough data while the processing unit is busy with previously received data. This may notably be a factor of a peak data bandwidth, which may be significantly higher than an average data bandwidth. The present invention, as described further below, is motivated by the insight that providing a buffer with a fixed capacity separately for each of multiple data streams may result in a memory array that may often be largely empty. This may be undesirable as on-chip memories can be an expensive resource, increasing die size and power consumption.
FIG. 1 schematically shows an example of a system on chip 10 in which a data source 12 sends a stream of data to a receiver 14. The receiver 14 transfers the data to a buffer 18 to be read by a processing unit 20. The buffer 18 may be located in a memory unit 16. The memory unit 16 may for example be an SRAM unit. The memory unit 16 may comprise a set of memory regions. Each memory region may comprise, for example, one or more registers. The memory regions may have the same capacity, e.g., a certain number of kilobytes, or they may have different capacities. In a variant of the shown example, there are multiple data sources similar to the shown data source 12 and each of these data sources 12 has a corresponding static buffer, similar to the shown buffer 18, assigned or connected to it.
An application, e.g., a process executed by the processing unit 20, may employ a virtualization mechanism to share a single physical resource among two or more virtual machines, effectively creating several, i.e. two or more, virtual channels on a single physical channel. In a common situation, these virtual machines may be unaware of each other and each may operate independently of the other virtual machines while a hypervisor unit or a super user unit arbitrates between the virtual machines. In such a situation, since each virtual machine “assumes” that it can use the full bandwidth of the physical channel, it may require a buffer having a size adapted to the full bandwidth of the physical channel, for each virtual machine. The total size of the set of buffers provided for the virtual machines is then proportional to the number of virtual machines.
FIG. 2 schematically shows another example of a SoC 10. In this example the SoC 10 comprises four data sources 12a to 12d sharing a single physical line for feeding their data to a processing unit 20. In the example, the processing unit 20 comprises processor cores 20a to 20d. The data sources 12a to 12d may provide data streams simultaneously. An arbitrator unit 22 of the SoC 10 may select one of the data streams and route it to the receiver 14. The receiver 14 may further provide it to the memory unit 16.
The memory unit 16 may comprise, for each of the data sources 12a to 12d, a separate buffer having a fixed capacity. The data sources 12a to 12d may thus be assigned buffers 18a, 18b, 18c, and 18d, respectively. Accordingly, when the arbitrator unit 22 has selected, for example, data source 12c as the active data source among the data sources 12a to 12d, the data stream from the selected data source, e.g., from data source 12c, may be routed to the processing unit 20 through the buffer, e g., buffer 18c, that belongs to the selected data source.
Comparing FIG. 2 to FIG. 1, it is noted that the data rate of the data received by the receiver 14 may be the same in both Figures. In spite of this, the total buffer capacity is four times as large in FIG. 2 as in FIG. 1, assuming that each of the buffers 18a to 18d has the same capacity as the buffer 18 in FIG. 1. However, considering that in both the example of FIG. 1 and the example of FIG. 2 the memory unit 16 receives the same amount of data per time from the receiver 14 it may be expected that the buffers 18a to 18d in FIG. 2 may on average be largely empty.
For example, a device with an Ethernet port, e.g., a one-GB-per-second-Ethernet port, supporting eight virtual channels and a priority-based flow control in accordance with the prior art may require providing a static buffer to each virtual channel wherein the buffer must be large enough to absorb the incoming data while the processor is busy with previously received data. In addition, an emergency buffer may be required to absorb the incoming data from the moment the processor has issued a pause frame to a transmitter on the other side until the flow of data stops. Assuming that the required buffer size to absorb the incoming data at the steady state is 256 KB, the buffer required to absorb peak traffic may be two to four times larger than that, i.e., at least 512 KB. Also assuming that the emergency buffer is 20 KB, the total buffer size required for each virtual channel may be 532 KB. Each of the virtual channels may require a dedicated buffer because it is not known beforehand how the data is distributed among the different virtual channels. Therefore a system designer must assume that at any given point in time any one of the virtual channels may have the full one GB per second bandwidth and therefore a memory array of eight times 532 KB, i.e., approximately 4 MB, must be provided.
Such a static allocation does not exploit the fact that the aggregated traffic on all 8 channels does not exceed the physical limit of one GB per second.